I2s clk gating

I2s clk gating definition. More...

Collaboration diagram for I2s clk gating:

Macros
#define	I2S_CLK_GATING_SEL_0_CYCLE   (0)
#define	I2S_CLK_GATING_SEL_12_CYCLE   (1)
#define	I2S_CLK_GATING_SEL_16_CYCLE   (2)
#define	I2S_CLK_GATING_SEL_24_CYCLE   (3)
#define	I2S_CLK_GATING_SEL_32_CYCLE   (4)

Detailed Description

I2s clk gating definition.

Macro Definition Documentation

I2S_CLK_GATING_SEL_0_CYCLE

#define I2S_CLK_GATING_SEL_0_CYCLE   (0)

No clock gating

I2S_CLK_GATING_SEL_12_CYCLE

#define I2S_CLK_GATING_SEL_12_CYCLE   (1)

Gate after 12 clock cycles

I2S_CLK_GATING_SEL_16_CYCLE

#define I2S_CLK_GATING_SEL_16_CYCLE   (2)

Gate after 16 clock cycles

I2S_CLK_GATING_SEL_24_CYCLE

#define I2S_CLK_GATING_SEL_24_CYCLE   (3)

Gate after 24 clock cycles

I2S_CLK_GATING_SEL_32_CYCLE

#define I2S_CLK_GATING_SEL_32_CYCLE   (4)

Gate after 32 clock cycles