pan_dmac.h

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/*
 * Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0 
 */
 
#ifndef __PAN_DMAC_H__
#define __PAN_DMAC_H__
 
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
 
 
#define DMAC_CHANNEL_NUMBER         (3)         
#define DMA_INVLID_CHANNEL          (~0ul)  
/*CTL register*/
 
#define DMAC_TransferType_Mem2Mem    (0)        
#define DMAC_TransferType_Mem2Per    (1)        
#define DMAC_TransferType_Per2Mem    (2)        
#define DMAC_TransferType_Per2Per    (3)        
#define DMAC_FlowControl_DMA         (0)        
#define DMAC_FlowControl_Peripheral  (1)        
#define DMAC_BurstLen_1              (0)        
#define DMAC_BurstLen_4              (1)        
#define DMAC_BurstLen_8              (2)        
#define DMAC_BurstLen_16             (3)        
#define DMAC_BurstLen_32             (4)        
#define DMAC_BurstLen_64             (5)        
#define DMAC_BurstLen_128            (6)        
#define DMAC_BurstLen_256            (7)        
#define DMAC_AddrChange_Increment   (0)     
#define DMAC_AddrChange_Decrement   (1)     
#define DMAC_AddrChange_NoChange    (2)     
#define DMAC_DataWidth_8            (0)     
#define DMAC_DataWidth_16           (1)     
#define DMAC_DataWidth_32           (2)     
#define DMAC_DataWidth_64           (3)     
#define DMAC_DataWidth_128          (4)     
#define DMAC_DataWidth_256          (5)     
#define DMAC_Peripheral_I2C0_Tx      (0)        
#define DMAC_Peripheral_I2C0_Rx      (1)        
#define DMAC_Peripheral_SPI0_Tx      (2)        
#define DMAC_Peripheral_SPI0_Rx      (3)        
#define DMAC_Peripheral_UART0_Tx     (4)        
#define DMAC_Peripheral_UART0_Rx     (5)        
#define DMAC_Peripheral_IIS_Tx       (6)        
#define DMAC_Peripheral_IIS_Rx       (7)        
#define DMAC_Peripheral_SPI1_Tx      (8)        
#define DMAC_Peripheral_SPI1_Rx      (9)        
#define DMAC_Peripheral_UART1_Tx     (10)       
#define DMAC_Peripheral_UART1_Rx     (11)       
#define DMAC_Peripheral_ADC                  (12)       
#define DMAC_HandshakePolarity_Low   (1)        
#define DMAC_HandshakePolarity_High  (0)        
#define DMAC_Handshake_Default       (1)        
#define DMAC_Handshake_Software      (1)        
#define DMAC_Handshake_Hardware      (0)        
#define DMAC_LockLevel_Tfr_Complete             (0)     
#define DMAC_LockLevel_Block_Complete           (1)     
#define DMAC_LockLevel_Transaction_Complete     (2)     
#define DMAC_ChannelPriority_0                  (0)     
#define DMAC_ChannelPriority_1                  (1)     
#define DMAC_ChannelPriority_2                  (2)     
#define DMAC_ChannelPriority_3                  (3)     
#define DMAC_ChannelPriority_4                  (4)     
#define DMAC_ChannelPriority_5                  (5)     
#define DMAC_ChannelPriority_6                  (6)     
#define DMAC_ChannelPriority_7                  (7)     
#define DMAC_CHANNELALL_MASK        (~((~0ul)<<DMAC_CHANNEL_NUMBER))        
#define DMAC_FLAG_INDEX_TFR         (0<<1)      
#define DMAC_FLAG_INDEX_BLK         (1<<1)      
#define DMAC_FLAG_INDEX_SRCTFR      (2<<1)      
#define DMAC_FLAG_INDEX_DSTTFR      (3<<1)      
#define DMAC_FLAG_INDEX_ERR         (4<<1)      
#define DMAC_FLAG_MASK_TFR          (1ul<<(DMAC_FLAG_INDEX_TFR   >>1))      
#define DMAC_FLAG_MASK_BLK          (1ul<<(DMAC_FLAG_INDEX_BLK   >>1))      
#define DMAC_FLAG_MASK_SRCTFR       (1ul<<(DMAC_FLAG_INDEX_SRCTFR>>1))      
#define DMAC_FLAG_MASK_DSTTFR       (1ul<<(DMAC_FLAG_INDEX_DSTTFR>>1))      
#define DMAC_FLAG_MASK_ERR          (1ul<<(DMAC_FLAG_INDEX_ERR   >>1))      
#define DMAC_FLAG_MASK_ALL          (0x1Ful)
typedef struct __DMAC_ChannelConfigTypeDef
{
    uint32_t CTL_L;
    uint32_t CTL_H;
    uint32_t CFG_L;
    uint32_t CFG_H;
}__DMAC_ChannelConfigTypeDef;
 
typedef struct DMAC_ChannelConfigTypeDef
{
    uint32_t IntEnable : 1;
    uint32_t DataWidthDst : 3;
    uint32_t DataWidthSrc : 3;
    uint32_t AddrChangeDst : 2;
    uint32_t AddrChangeSrc : 2; 
    uint32_t BurstLenDst : 3;
    uint32_t BurstLenSrc : 3;
    uint32_t GatherEnSrc : 1;
    uint32_t ScatterEnDst : 1;
    uint32_t __Rev0 : 1;
    uint32_t TransferType : 2;
    uint32_t FlowControl : 1;
    uint32_t __Rev1 : 9;
 
    uint32_t BlockSize : 12;
    uint32_t Done : 1; 
    uint32_t __Rev2 : 19;
 
    uint32_t __Rev3 : 5;
    uint32_t ChannelPriority : 3;
    uint32_t ChannelSuspend : 1;
    uint32_t FifoEmpty : 1;
    uint32_t HandshakeDst : 1;
    uint32_t HandshakeSrc : 1;
    uint32_t LockBus : 1;
    uint32_t LockChannel : 1;
    uint32_t LockBusLevel : 2;
    uint32_t LockChannelLevel : 2;
    uint32_t HandshakePolarityDst : 1;
    uint32_t HandshakePolaritySrc : 1;
    uint32_t __Rev4 : 10;
    uint32_t AutoReloadSrc : 1;
    uint32_t AutoReloadDst : 1;
 
    uint32_t FlowControlMode : 1;
    uint32_t FifoMode : 1;
    uint32_t ProtectControl : 3;
    uint32_t __Rev5 : 2;
    uint32_t PeripheralSrc : 4;
    uint32_t PeripheralDst : 4;
    uint32_t __Rev6 : 17;
}DMAC_ChannelConfigTypeDef;
 
__STATIC_INLINE uint32_t DMAC_IsChannelValid(DMA_T* dma,uint32_t ChIdx)
{
    return (ChIdx < DMAC_CHANNEL_NUMBER ? 1 : 0);
}
#define DMAC_ChannelMask(idx)       (1ul<<(idx))
__STATIC_INLINE uint32_t DMAC_CombinedIntStatus(DMA_T* dma,uint32_t FlgMsk)
{
    return (dma->STATUS_INT_L & FlgMsk ? 1 : 0);
}
__STATIC_INLINE uint32_t DMAC_StatusFlag(DMA_T* dma,uint32_t ChIdx,uint32_t FlgIdx)
{
    return ((__IO uint32_t*)(&dma->RAW_TFR_L))[FlgIdx]&(0x1<<ChIdx) ? 1 : 0;
}
 
__STATIC_INLINE uint32_t DMAC_IntFlag(DMA_T* dma,uint32_t ChIdx,uint32_t FlgIdx)
{
    return ((__IO uint32_t*)(&dma->STATUS_TFR_L))[FlgIdx]&(0x1<<ChIdx) ? 1 : 0;
}
 
__STATIC_INLINE uint32_t DMAC_IntFlagMsk(DMA_T* dma,uint32_t ChIdx,uint32_t FlgIdx)
{
    return ((__IO uint32_t*)(&dma->MSK_TFR_L))[FlgIdx]&(0x1<<ChIdx) ? 1 : 0;
}
 
__STATIC_INLINE void DMAC_ClrIntFlag(DMA_T* dma,uint32_t ChIdx,uint32_t FlgIdx)
{
    ((__IO uint32_t*)(&dma->CLEAR_TFR_L))[FlgIdx]= (0x1<<ChIdx);
}
 
void DMAC_Init(DMA_T * dma);
 
void DMAC_DeInit(DMA_T * dma);
 
void DMAC_ClrIntFlagMsk(DMA_T* dma, uint32_t ChIdx, uint32_t FlgIdx);
 
void DMAC_SetIntFlagMsk(DMA_T* dma, uint32_t ChIdx, uint32_t FlgIdx);
 
void DMAC_SetChannelConfig(DMA_T * dma,uint32_t ChIdx,DMAC_ChannelConfigTypeDef *Config);
 
void DMAC_GetChannelConfig(DMA_T * dma,uint32_t ChIdx,DMAC_ChannelConfigTypeDef *Config);
 
void DMAC_StartChannel(DMA_T * dma,uint32_t ChIdx,void* Src,void* Dst,uint32_t Len);
 
void DMAC_StopChannel(DMA_T * dma,uint32_t ChIdx);
 
uint32_t DMAC_AcquireChannel(DMA_T * dma);
 
void DMAC_ReleaseChannel(DMA_T * dma, uint32_t ChIdx);
 
 
#ifdef __cplusplus
}
#endif /* __cplusplus */
 
#endif /* __PAN_DMAC_H__ */