pan_clk.h

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/*
 * Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0 
 */
 
#ifndef __PAN_CLK_H__
#define __PAN_CLK_H__
 
#ifdef __cplusplus
extern "C"
{
#endif
 
 
 
#define CLK_DPLL_OUTPUT_DIV     (CLK_DPLL_OUT_96M)              
#define CLK_APB1_WDTSEL_MILLI_PULSE             (0x00000000UL)  
#define CLK_APB1_WDTSEL_RCL32K                  (0x00010000UL)  
#define CLK_APB1_WWDTSEL_MILLI_PULSE            (0x00000000UL)  
#define CLK_APB1_WWDTSEL_RCL32K                 (0x00020000UL)  
#define CLK_APB1_TMR0SEL_APB1CLK                (0x00000000UL)  
#define CLK_APB1_TMR0SEL_RCL32K                 (0x00040000UL)  
#define CLK_APB1_TMR0SEL_TM0                    (0x00080000UL)  
#define CLK_APB2_TMR1SEL_APB2CLK                (0x00000000UL)  
#define CLK_APB2_TMR1SEL_RCL32K                 (0x00000100UL)  
#define CLK_APB2_TMR1SEL_TM1                    (0x00000200UL)  
#define CLK_APB2_TMR2SEL_APB2CLK                (0x00000000UL)  
#define CLK_APB2_TMR2SEL_RCL32K                 (0x00000400UL)  
#define CLK_APB2_TMR2SEL_TM2                    (0x00000800UL)  
 #define FREQ_1MHZ                            (1000000)         
 #define FREQ_8MHZ                            (8000000)         
 #define FREQ_16MHZ                           (16000000)        
 #define FREQ_25MHZ                           (25000000)        
 #define FREQ_32MHZ                           (32000000)        
 #define FREQ_48MHZ                           (48000000)        
 #define FREQ_64MHZ                           (64000000)        
 #define FREQ_96MHZ                           (96000000)        
 #define FREQ_50MHZ                           (50000000)        
 #define FREQ_72MHZ                           (72000000)        
 #define FREQ_100MHZ                          (100000000)       
 #define FREQ_200MHZ                          (200000000)       
 #define FREQ_250MHZ                          (250000000)       
 #define FREQ_500MHZ                          (500000000)       
#define CLK_SYS_SRCSEL_RCH                    ((uint32_t)0x00000000)  
#define CLK_SYS_SRCSEL_XTH                    ((uint32_t)0x00000100)  
#define CLK_SYS_SRCSEL_DPLL                     ((uint32_t)0x00000200)  
#define CLK_DPLL_REF_CLKSEL_RCH               ((uint32_t)0x00000000)    
#define CLK_DPLL_REF_CLKSEL_XTH               ((uint32_t)0x00000002)    
#define CLK_DPLL_OUT_48M                    ((uint32_t)0x00000000)    
#define CLK_DPLL_OUT_64M                      ((uint32_t)0x00000001)    
#define CLK_HCLK_APB2_Div1                    ((uint32_t)0x00000000)  
#define CLK_HCLK_APB2_Div2                    ((uint32_t)0x00100000)  
#define CLK_HCLK_APB2_Div4                    ((uint32_t)0x00200000)  
#define CLK_HCLK_APB2_Div8                    ((uint32_t)0x00400000)  
#define CLK_HCLK_APB2_Div16                   ((uint32_t)0x00800000)  
#define CLK_HCLK_APB1_Div1                    ((uint32_t)0x00000000)  
#define CLK_HCLK_APB1_Div2                    ((uint32_t)0x00010000)  
#define CLK_HCLK_APB1_Div4                    ((uint32_t)0x00020000)  
#define CLK_HCLK_APB1_Div8                    ((uint32_t)0x00040000)  
#define CLK_HCLK_APB1_Div16                   ((uint32_t)0x00080000)  
#define CLK_APB1Periph_I2C0               ((uint32_t)0x00000001)      
#define CLK_APB1Periph_SPI0               ((uint32_t)0x00000002)      
#define CLK_APB1Periph_UART0              ((uint32_t)0x00000008)      
#define CLK_APB1Periph_PWM0_CH01          ((uint32_t)0x00000010)      
#define CLK_APB1Periph_PWM0_CH23          ((uint32_t)0x00000020)      
#define CLK_APB1Periph_PWM0_CH45          ((uint32_t)0x00000040)      
#define CLK_APB1Periph_PWM0_CH67          ((uint32_t)0x00000080)      
#define CLK_APB1Periph_PWM0_EN            ((uint32_t)0x00000100)      
#define CLK_APB1Periph_ADC                ((uint32_t)0x00000200)      
#define CLK_APB1Periph_WDT                ((uint32_t)0x00000400)      
#define CLK_APB1Periph_WWDT               ((uint32_t)0x00000800)      
#define CLK_APB1Periph_TMR0               ((uint32_t)0x00001000)      
#define CLK_APB1Periph_I2SS               ((uint32_t)0x00100000)      
#define CLK_APB1Periph_I2SM               ((uint32_t)0x00200000)      
#define CLK_APB1Periph_PWM1_CH01          ((uint32_t)0x00400000)      
#define CLK_APB1Periph_PWM1_CH23          ((uint32_t)0x00800000)      
#define CLK_APB1Periph_PWM1_CH45          ((uint32_t)0x01000000)      
#define CLK_APB1Periph_PWM1_CH67          ((uint32_t)0x02000000)      
#define CLK_APB1Periph_PWM1_EN            ((uint32_t)0x04000000)      
#define CLK_APB1Periph_PWM2_CH01          ((uint32_t)0x08000000)      
#define CLK_APB1Periph_PWM2_CH23          ((uint32_t)0x10000000)      
#define CLK_APB1Periph_PWM2_CH45          ((uint32_t)0x20000000)      
#define CLK_APB1Periph_PWM2_CH67          ((uint32_t)0x40000000)      
#define CLK_APB1Periph_PWM2_EN            ((uint32_t)0x80000000)      
#define CLK_APB1Periph_All                ((uint32_t)0xfff01ffb)      
#define CLK_APB2Periph_SPI1               ((uint32_t)0x00000002)      
#define CLK_APB2Periph_UART1              ((uint32_t)0x00000008)      
#define CLK_APB2Periph_TMR1               ((uint32_t)0x00000010)      
#define CLK_APB2Periph_TMR2               ((uint32_t)0x00000020)      
#define CLK_APB2Periph_KEYSCAN            ((uint32_t)0x00001000)      
#define CLK_APB2Periph_QDEC               ((uint32_t)0x00400000)      
#define CLK_APB2Periph_All                ((uint32_t)0x0040103a)      
#define CLK_AHBPeriph_DMAC                ((uint32_t)0x00000001)      
#define CLK_AHBPeriph_GPIO                ((uint32_t)0x00000002)      
#define CLK_AHBPeriph_SYSTICK             ((uint32_t)0x00000004)      
#define CLK_AHBPeriph_APB1                ((uint32_t)0x00000008)      
#define CLK_AHBPeriph_APB2                ((uint32_t)0x00000010)      
#define CLK_AHBPeriph_AHB                 ((uint32_t)0x00000020)      
#define CLK_AHBPeriph_BLE_32M             ((uint32_t)0x00000040)      
#define CLK_AHBPeriph_BLE_32K             ((uint32_t)0x00000080)      
#define CLK_AHBPeriph_ROM                 ((uint32_t)0x00000400)      
#define CLK_AHBPeriph_EFUSE               ((uint32_t)0x00000800)      
#define CLK_AHBPeriph_ECC                 ((uint32_t)0x00001000)      
#define CLK_AHBPeriph_USB_AHB             ((uint32_t)0x00002000)      
#define CLK_AHBPeriph_USB_48M             ((uint32_t)0x00004000)      
#define CLK_AHBPeriph_All                 ((uint32_t)0x00007CFF)      
#define CLK_RCL_SELECT                    (0)    
#define CLK_RCH_SELECT                    (1)    
#define CLK_XTL_SELECT                    (2)    
#define CLK_XTH_SELECT                    (3)    
#define CLK_DPLL_SELECT                   (4)    
#define CLK_STABLE_STATUS_Pos             (24)  
#define CLK_STABLE_STATUS_Msk             (0x1ul << CLK_STABLE_STATUS_Pos)    
#define CLKTRIM_CALC_CLK_SEL_32K          (0)       
#define CLKTRIM_CALC_CLK_SEL_32M          (1)       
#define CLKTRIM_CALC_CLK_SEL_EXT          (3)       
#define CLKTRIM_QDEC_CLK_SEL_APB          (0)       
#define CLKTRIM_QDEC_CLK_SEL_32K          (1)       
#define CLKTRIM_KSCAN_CLK_SEL_APB         (0)       
#define CLKTRIM_KSCAN_CLK_SEL_32K         (1)       
__STATIC_INLINE void CLK_XthStartupConfig(void)
{
    CLK->XTH_CTRL |= (CLK_XTHCTL_FSYN_EN_Msk | CLK_XTHCTL_START_FAST_Msk);
}
 
__STATIC_INLINE void CLK_HCLK1Config(uint32_t u32ClkDiv)
{
    CLK->CLK_TOP_CTRL = (CLK->CLK_TOP_CTRL & (~CLK_TOPCTL_AHB_DIV_Msk)) | (u32ClkDiv << CLK_TOPCTL_AHB_DIV_Pos);
}
 
__STATIC_INLINE void CLK_PCLK1Config(uint32_t u32ClkDiv )
{
    CLK->CLK_TOP_CTRL = (CLK->CLK_TOP_CTRL & (~CLK_TOPCTL_APB1_DIV_Msk))| (u32ClkDiv << CLK_TOPCTL_APB1_DIV_Pos);
}
 
__STATIC_INLINE void CLK_PCLK2Config(uint32_t u32ClkDiv)
{
    CLK->CLK_TOP_CTRL = (CLK->CLK_TOP_CTRL & (~CLK_TOPCTL_APB2_DIV_Msk))| (u32ClkDiv << CLK_TOPCTL_APB2_DIV_Pos);
}
 
__STATIC_INLINE void CLK_SetQdecDiv(uint32_t div)
{
    CLK->APB2_CLK_CTRL = (CLK->APB2_CLK_CTRL & ~CLK_APB2CLK_QDEC_DIV_Msk) | (div << CLK_APB2CLK_QDEC_DIV_Pos);
}
 
__STATIC_INLINE uint32_t CLK_GetQdecDiv(void)
{
    return ((CLK->APB2_CLK_CTRL & CLK_APB2CLK_QDEC_DIV_Msk) >> CLK_APB2CLK_QDEC_DIV_Pos);
}
__STATIC_INLINE void CLK_SetQdecClkSrc(uint32_t src)
{
    CLK->APB2_CLK_CTRL1 = (CLK->APB2_CLK_CTRL1 & ~CLK_APB2CLK_QDEC_CLK_SEL_Msk) | (src << CLK_APB2CLK_QDEC_CLK_SEL_Pos);
}
__STATIC_INLINE void CLK_SetKeyscanDiv(uint32_t div)
{
    CLK->APB2_CLK_CTRL = (CLK->APB2_CLK_CTRL & ~CLK_APB2CLK_KEYSCAN_DIV_Msk) | (div << CLK_APB2CLK_KEYSCAN_DIV_Pos);
}
__STATIC_INLINE uint32_t CLK_GetKeyscanDiv(void)
{
    return ((CLK->APB2_CLK_CTRL & CLK_APB2CLK_KEYSCAN_DIV_Msk) >> CLK_APB2CLK_KEYSCAN_DIV_Pos);
}
__STATIC_INLINE void CLK_SetKeyscanClkSrc(uint32_t src)
{
    CLK->APB2_CLK_CTRL1 = (CLK->APB2_CLK_CTRL1 & ~CLK_APB2CLK_KSCAN_CLK_DIV_Msk) | (src << CLK_APB2CLK_KSCAN_CLK_DIV_Pos);
}
 
 
__STATIC_INLINE void CLK_SetDpllOutputFreq(uint32_t freq)
{
    CLK->DPLL_CTRL &= ~CLK_DPLLCTL_FREQ_OUT_Msk;
    CLK->DPLL_CTRL |= freq;
}
 
__STATIC_INLINE void CLK_SetTemperatureGain(uint32_t gain)
{
    ANA->ANA_TEMP = (ANA->ANA_TEMP & ~ANAC_TEMP_GAIN_CTL_Msk) | (gain<<ANAC_TEMP_GAIN_CTL_Pos);
}
 
__STATIC_INLINE void CLK_EnableTempDetect(void)
{
        ANA->ANA_TEMP |= ANAC_TEMP_ENABLE_Msk;
}
 
 
__STATIC_INLINE void CLK_EnableClkTrim(FunctionalState NewState)
{
    (NewState != ENABLE)?(CLK->APB2_CLK_CTRL1 &= ~CLK_APB2CLK_TRIM_EN_Msk):(CLK->APB2_CLK_CTRL1 |= CLK_APB2CLK_TRIM_EN_Msk);
}
 
__STATIC_INLINE void CLK_EnableClkTrimCalc(FunctionalState NewState)
{
    (NewState != ENABLE)?(CLK->APB2_CLK_CTRL1 &= ~CLK_APB2CLK_TRIM_CALC_EN_Msk):(CLK->APB2_CLK_CTRL1 |= CLK_APB2CLK_TRIM_CALC_EN_Msk);
}
 
__STATIC_INLINE void CLK_SelectClkTrimSrc(uint32_t src)
{
    CLK->APB2_CLK_CTRL1 = (CLK->APB2_CLK_CTRL1 & ~CLK_APB2CLK_CALC_CLK_SEL_Msk)| (src << CLK_APB2CLK_CALC_CLK_SEL_Pos);
}
 
__STATIC_INLINE void CLK_SetClkTrimCalClkDiv(uint16_t div)
{
    uint32_t reg = CLK->APB2_CLK_CTRL1 & ~CLK_APB2CLK_CALC_CLK_DIV_Msk;
    CLK->APB2_CLK_CTRL1 = reg | ((div << CLK_APB2CLK_CALC_CLK_DIV_Pos) & CLK_APB2CLK_CALC_CLK_DIV_Msk);
}
 
 
enum
{
    CLK_FLASH_CLKDIV_1  = 0x00, 
    CLK_FLASH_CLKDIV_2  = 0x01, 
    CLK_FLASH_CLKDIV_4  = 0x02, 
    CLK_FLASH_CLKDIV_8  = 0x04, 
    CLK_FLASH_CLKDIV_16 = 0x08, 
    CLK_FLASH_CLKDIV_32 = 0x10, 
};
 
__STATIC_FORCEINLINE void CLK_SetFlashClkDiv(uint8_t div)
{
    uint32_t reg = CLK->AHB_CLK_CTRL & (~CLK_AHBCLK_SPI_FLASH_DIV_Msk);
    CLK->AHB_CLK_CTRL = reg | ((div << CLK_AHBCLK_SPI_FLASH_DIV_Pos) & CLK_AHBCLK_SPI_FLASH_DIV_Msk);
}
 
uint32_t CLK_GetHCLKFreq(void);
 
uint32_t CLK_GetCPUFreq(void);
 
uint32_t CLK_GetPCLK1Freq(void);
 
uint32_t CLK_GetPCLK2Freq(void);
 
void CLK_RefClkSrcConfig(uint32_t u32ClkSrc);
void CLK_SYSCLKConfig(uint32_t u32ClkSrc,uint32_t freq_out);
void CLK_HCLKConfig(uint32_t u32ClkDiv);
void CLK_PCLK1Config(uint32_t u32ClkDiv );
void CLK_PCLK2Config(uint32_t u32ClkDiv);
 
void CLK_AHBPeriphClockCmd(uint32_t CLK_AHBPeriph, FunctionalState NewState);
 
void CLK_APB1PeriphClockCmd(uint32_t CLK_APB1Periph, FunctionalState NewState);
 
void CLK_APB2PeriphClockCmd(uint32_t CLK_APB2Periph, FunctionalState NewState);
 
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
 
uint32_t CLK_Wait3vSyncReady(void);
 
void CLK_Set3vSyncAuto(void);
void CLK_SetWdtClkSrc(uint32_t u32clksel);
 
void CLK_SetWwdtClkSrc(uint32_t u32clksel);
 
void CLK_SetTmrClkSrc(TIMER_T *timer, uint32_t u32clksel);
 
uint32_t CLK_GetPeripheralFreq(void * Peripheral);
 
#define DISABLE_3V_AUTOSYNC       ANA->LP_REG_SYNC &= ~ANAC_LP_REG_AUTOSYNC_Msk
#define ENABLE_3V_AUTOSYNC        ANA->LP_REG_SYNC |= ~ANAC_LP_REG_AUTOSYNC_Msk
#define START_3V_SYNC_NBLOCK      ANA->LP_REG_SYNC |= ANAC_LP_REG_SYNC_3V_Msk
 
#ifdef __cplusplus
}
#endif
 
#endif /* __PAN_CLK_H__ */