pan_uart.h

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/*
 * Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0 
 */
 
#ifndef __PAN_UART_H__
#define __PAN_UART_H__
 
#ifdef __cplusplus
extern "C"
{
#endif
 
 
 
typedef enum UART_TxTrigger
{
    UART_TX_FIFO_EMPTY              = 0x0,
    UART_TX_FIFO_TWO_CHARS          = 0x1,
    UART_TX_FIFO_QUARTER_FULL       = 0x2,
    UART_TX_FIFO_HALF_FULL          = 0x3
} UART_TxTriggerDef;
typedef enum UART_RxTrigger
{
    UART_RX_FIFO_ONE_CHAR           = 0x0,
    UART_RX_FIFO_QUARTER_FULL       = 0x1,
    UART_RX_FIFO_HALF_FULL          = 0x2,
    UART_RX_FIFO_TWO_LESS_THAN_FULL = 0x3
} UART_RxTriggerDef;
typedef enum UART_LineCtrl
{
    Uart_Line_5n1       = 0x00,     
    Uart_Line_5n1_5     = 0x04,     
    Uart_Line_5e1       = 0x18,     
    Uart_Line_5e1_5     = 0x1c,     
    Uart_Line_5o1       = 0x08,     
    Uart_Line_5o1_5     = 0x0c,     
    Uart_Line_5s1       = 0x38,     
    Uart_Line_5s1_5     = 0x3c,     
    Uart_Line_5m1       = 0x28,     
    Uart_Line_5m1_5     = 0x2c,     
    Uart_Line_6n1       = 0x01,     
    Uart_Line_6n2       = 0x05,     
    Uart_Line_6e1       = 0x19,     
    Uart_Line_6e2       = 0x1d,     
    Uart_Line_6o1       = 0x09,     
    Uart_Line_6o2       = 0x0d,     
    Uart_Line_6s1       = 0x39,     
    Uart_Line_6s2       = 0x3d,     
    Uart_Line_6m1       = 0x29,     
    Uart_Line_6m2       = 0x2d,     
    Uart_Line_7n1       = 0x02,     
    Uart_Line_7n2       = 0x06,     
    Uart_Line_7e1       = 0x1a,     
    Uart_Line_7e2       = 0x1e,     
    Uart_Line_7o1       = 0x0a,     
    Uart_Line_7o2       = 0x0e,     
    Uart_Line_7s1       = 0x3a,     
    Uart_Line_7s2       = 0x3e,     
    Uart_Line_7m1       = 0x2a,     
    Uart_Line_7m2       = 0x2e,     
    Uart_Line_8n1       = 0x03,     
    Uart_Line_8n2       = 0x07,     
    Uart_Line_8e1       = 0x1b,     
    Uart_Line_8e2       = 0x1f,     
    Uart_Line_8o1       = 0x0b,     
    Uart_Line_8o2       = 0x0f,     
    Uart_Line_8s1       = 0x3b,     
    Uart_Line_8s2       = 0x3f,     
    Uart_Line_8m1       = 0x2b,     
    Uart_Line_8m2       = 0x2f,     
} UART_LineCtrlDef;
typedef enum UART_Irq
{
    UART_IRQ_RECV_DATA_AVL  = 0x01,     
    UART_IRQ_THR_EMPTY      = 0x02,     
    UART_IRQ_LINE_STATUS    = 0x04,     
    UART_IRQ_MODEM_STATUS   = 0x08,     
    UART_IRQ_ALL            = 0x0f      
} UART_IrqDef;
typedef enum UART_Event
{
    UART_EVENT_MODEM        = 0x0,  
    UART_EVENT_NONE         = 0x1,  
    UART_EVENT_THR_EMPTY    = 0x2,  
    UART_EVENT_DATA         = 0x4,  
    UART_EVENT_LINE         = 0x6,  
#if 0
    UART_EVENT_BUSY         = 0x7,  
#endif
    UART_EVENT_TIMEOUT      = 0xc   
} UART_EventDef;
typedef enum UART_LineStatus
{
    UART_LINE_DATA_RDY          = 0x01,     
    UART_LINE_OVERRUN_ERR       = 0x02,     
    UART_LINE_PARITY_ERR        = 0x04,     
    UART_LINE_FRAME_ERR         = 0x08,     
    UART_LINE_BREAK_INT         = 0x10,     
    UART_LINE_THRE              = 0x20,     
    UART_LINE_TXSR_EMPTY        = 0x40,     
    UART_LINE_RECV_FIFO_EMPTY   = 0x80,     
    UART_LINE_ADDR_RCVD         = 0x100     
} UART_LineStatusDef;
typedef enum UART_ModemStatus
{
    UART_MODEM_DCTS     = 0x01,     
    UART_MODEM_DDSR     = 0x02,     
    UART_MODEM_TERI     = 0x04,     
    UART_MODEM_DDCD     = 0x08,     
    UART_MODEM_CTS      = 0x10,     
    UART_MODEM_DSR      = 0x20,     
    UART_MODEM_RI       = 0x40,     
    UART_MODEM_DCD      = 0x80      
} UART_ModemStatusDef;
typedef struct
{
    uint32_t UART_BaudRate;             // set initial baudrate
    UART_LineCtrlDef UART_LineCtrl;     // set initial line control parameter
} UART_InitTypeDef;
 
 
 
 
__STATIC_INLINE void UART_EnableStickParity(UART_T* UARTx)
{
    UARTx->LCR |= UART_LCR_SP_Msk;
}
 
__STATIC_INLINE void UART_DisableStickParity(UART_T* UARTx)
{
    UARTx->LCR &= ~UART_LCR_SP_Msk;
}
 
__STATIC_INLINE UART_LineStatusDef UART_GetLineStatus(UART_T* UARTx)
{
    return (UART_LineStatusDef)(UARTx->LSR & UART_LSR_LINE_STATUS_Msk);
}
 
__STATIC_INLINE UART_ModemStatusDef UART_GetModemStatus(UART_T* UARTx)
{
    return (UART_ModemStatusDef)(UARTx->MSR & UART_MSR_MODEM_STATUS_Msk);
}
 
__STATIC_INLINE void UART_EnableFifo(UART_T* UARTx)
{
    // SCR(r/w) stores a copy of FCR(wo)
    UARTx->SCR |= UART_FCR_FIFOE_Msk;
 
    UARTx->IIR_FCR = UARTx->SCR;
}
 
__STATIC_INLINE void UART_DisableFifo(UART_T* UARTx)
{
    // SCR(r/w) stores a copy of FCR(wo)
    UARTx->SCR &= ~UART_FCR_FIFOE_Msk;
 
    UARTx->IIR_FCR = UARTx->SCR;
}
 
__STATIC_INLINE bool UART_IsFifoEnabled(UART_T* UARTx)
{
    return (UARTx->IIR_FCR & UART_IIR_FIFOSE_Msk) ? true : false;
}
 
__STATIC_INLINE void UART_ResetRxFifo(UART_T* UARTx)
{
    // SCR(r/w) stores a copy of FCR(wo)
    UARTx->SCR |= UART_FCR_RFIFOR_Msk;
 
    UARTx->IIR_FCR = UARTx->SCR;
    UARTx->SCR &= ~UART_FCR_RFIFOR_Msk; //Clear RFIFOR bit in SCR after use
 
    // Read Rx FIFO once again to de-assert rx interrupt if there is
    volatile uint32_t val = UARTx->RBR_THR_DLL;
    val = val;
}
 
__STATIC_INLINE void UART_ResetTxFifo(UART_T* UARTx)
{
    // SCR(r/w) stores a copy of FCR(wo)
    UARTx->SCR |= UART_FCR_XFIFOR_Msk;
 
    UARTx->IIR_FCR = UARTx->SCR;
    UARTx->SCR &= ~UART_FCR_XFIFOR_Msk; //Clear XFIFOR bit in SCR after use
}
 
__STATIC_INLINE void UART_SetTxTrigger(UART_T* UARTx, UART_TxTriggerDef level)
{
    // SCR(r/w) stores a copy of FCR(wo)
    UARTx->SCR &= ~UART_FCR_TET_Msk;
    UARTx->SCR |= (level << UART_FCR_TET_Pos);
 
    UARTx->IIR_FCR = UARTx->SCR;
}
 
 
__STATIC_INLINE void UART_SetRxTrigger(UART_T* UARTx, UART_RxTriggerDef level)
{
    // SCR(r/w) stores a copy of FCR(wo)
    UARTx->SCR &= ~UART_FCR_RT_Msk;
    UARTx->SCR |= (level << UART_FCR_RT_Pos);
 
    UARTx->IIR_FCR = UARTx->SCR;
}
 
__STATIC_INLINE uint8_t UART_GetTxFifoLevel(UART_T* UARTx)
{
    return (uint8_t)((UARTx->TFL & UART_TFL_Msk) >> UART_TFL_Pos);
}
 
__STATIC_INLINE uint8_t UART_GetRxFifoLevel(UART_T* UARTx)
{
     return (uint8_t)((UARTx->RFL & UART_RFL_Msk) >> UART_RFL_Pos);
}
 
__STATIC_INLINE void UART_EnableAfc(UART_T *UARTx)
{
    UARTx->MCR |= UART_MCR_AFCE_Msk;
}
 
__STATIC_INLINE void UART_DisableAfc(UART_T *UARTx)
{
    UARTx->MCR &= ~UART_MCR_AFCE_Msk;
}
 
__STATIC_INLINE bool UART_IsAfcEnabled(UART_T *UARTx)
{
    return (UARTx->MCR & UART_MCR_AFCE_Msk) ? true : false;
}
 
__STATIC_INLINE void UART_SendData(UART_T* UARTx, uint8_t Data)
{
    UARTx->RBR_THR_DLL = Data;
}
 
__STATIC_INLINE uint8_t UART_ReceiveData(UART_T* UARTx)
{
    return (uint8_t)UARTx->RBR_THR_DLL;
}
 
__STATIC_INLINE void UART_EnablePtime(UART_T* UARTx)
{
    UARTx->IER_DLH |= UART_IER_EPTI_Msk;
}
 
__STATIC_INLINE void UART_DisablePtime(UART_T* UARTx)
{
    UARTx->IER_DLH &= ~UART_IER_EPTI_Msk;
}
 
__STATIC_INLINE bool UART_IsPtimeEnabled(UART_T* UARTx)
{
    return (UARTx->IER_DLH & UART_IER_EPTI_Msk) ? true : false;
}
 
__STATIC_INLINE void UART_EnableIrq(UART_T* UARTx, UART_IrqDef irq)
{
    UARTx->IER_DLH |= ((irq << UART_IER_ALL_IRQ_Pos) & UART_IER_ALL_IRQ_Msk);
}
 
__STATIC_INLINE void UART_DisableIrq(UART_T* UARTx, UART_IrqDef irq)
{
    UARTx->IER_DLH &= ~((irq << UART_IER_ALL_IRQ_Pos) & UART_IER_ALL_IRQ_Msk);
}
 
__STATIC_INLINE bool UART_IsIrqEnabled(UART_T* UARTx, UART_IrqDef irq)
{
    return (UARTx->IER_DLH & ((irq << UART_IER_ALL_IRQ_Pos) & UART_IER_ALL_IRQ_Msk)) ? true : false;
}
 
__STATIC_INLINE uint8_t UART_GetIrqMasked(UART_T* UARTx)
{
    return (uint8_t)((UARTx->IER_DLH & UART_IER_ALL_IRQ_Msk) >> UART_IER_ALL_IRQ_Pos);
}
 
__STATIC_INLINE UART_EventDef UART_GetActiveEvent(UART_T * UARTx)
{
    return (UART_EventDef)((UARTx->IIR_FCR & UART_IIR_IID_Msk) >> UART_IIR_IID_Pos);
}
 
__STATIC_INLINE bool UART_IsTxFifoEmpty(UART_T* UARTx)
{
    return (UARTx->USR & UART_USR_TFE_Msk) ? true : false;
}
 
__STATIC_INLINE bool UART_IsTxFifoFull(UART_T* UARTx)
{
    return (UARTx->USR & UART_USR_TFNF_Msk) ? false : true;
}
 
__STATIC_INLINE bool UART_IsRxFifoEmpty(UART_T* UARTx)
{
    return (UARTx->USR & UART_USR_RFNE_Msk) ? false : true;
}
 
__STATIC_INLINE bool UART_IsRxFifoFull(UART_T* UARTx)
{
    return (UARTx->USR & UART_USR_RFF_Msk) ? true : false;
}
 
__STATIC_INLINE void UART_EnableHaltTX(UART_T* UARTx)
{
    UARTx->HTX = 0x1;
}
 
__STATIC_INLINE void UART_DisableHaltTX(UART_T* UARTx)
{
    UARTx->HTX = 0x0;
}
 
__STATIC_INLINE void UART_EnableRts(UART_T* UARTx)
{
    UARTx->MCR |= UART_MCR_RTS_Msk;
}
 
__STATIC_INLINE void UART_DisableRts(UART_T* UARTx)
{
    UARTx->MCR &= ~UART_MCR_RTS_Msk;
}
 
__STATIC_INLINE void UART_Enable9BitData( UART_T* UARTx)
{
    UARTx->LCR_EXT |= UART_LCR_EXT_DLS_E_Msk;
}
 
__STATIC_INLINE void UART_Disable9BitData( UART_T* UARTx)
{
    UARTx->LCR_EXT &= ~UART_LCR_EXT_DLS_E_Msk;
}
 
__STATIC_INLINE void UART_EnableAddrMatchMode(UART_T* UARTx)
{
   UARTx->LCR_EXT |= UART_LCR_EXT_ADDR_MATCH_Msk;
}
 
__STATIC_INLINE void UART_DisableAddrMatchMode(UART_T* UARTx)
{
   UARTx->LCR_EXT &= ~UART_LCR_EXT_ADDR_MATCH_Msk;
}
 
__STATIC_INLINE void UART_SendAddr(UART_T* UARTx)
{
   UARTx->LCR_EXT |= UART_LCR_EXT_SEND_ADDR_Msk;
}
 
__STATIC_INLINE void UART_SetReceiveAddress( UART_T* UARTx,uint32_t addr)
{
    UARTx->RAR = addr;
}
 
__STATIC_INLINE void UART_SetTransmitAddress( UART_T* UARTx,uint32_t addr)
{
    UARTx->TAR = addr;
}
 
extern bool UART_Init(UART_T* UARTx, UART_InitTypeDef* UART_InitStruct);
extern void UART_DeInit(UART_T* UARTx );
 
extern bool UART_SendMultipleData(UART_T* UARTx, uint8_t* Buf, size_t BufSize, size_t SendSize);
 
extern bool UART_ReceiveMultipleData(UART_T* UARTx, uint8_t* Buf, size_t BufSize, size_t ExpectSize);
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* __PAN_UART_H__ */