pan_spi.h

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/*
 * Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0 
 */
 
#ifndef __PAN_SPI_H__
#define __PAN_SPI_H__
 
#ifdef __cplusplus
extern "C"
{
#endif
 
typedef enum SPI_Irq
{
    SPI_IRQ_TX_HALF_EMPTY   = 0x08,     
    SPI_IRQ_RX_HALF_FULL    = 0x04,     
    SPI_IRQ_RX_TIMEOUT      = 0x02,     
    SPI_IRQ_RX_OVERRUN      = 0x01,     
    SPI_IRQ_ALL             = 0x0f      
} SPI_IrqDef;
typedef enum SPI_Role
{
    SPI_RoleMaster  = 0x0,      
    SPI_RoleSlave   = 0x1           
} SPI_RoleDef;  
typedef enum SPI_DataFrameSize
{
    SPI_DataFrame_4b    = 0x03,
    SPI_DataFrame_5b    = 0x04,
    SPI_DataFrame_6b    = 0x05,
    SPI_DataFrame_7b    = 0x06,
    SPI_DataFrame_8b    = 0x07,
    SPI_DataFrame_9b    = 0x08,
    SPI_DataFrame_10b   = 0x09,
    SPI_DataFrame_11b   = 0x0a,
    SPI_DataFrame_12b   = 0x0b,
    SPI_DataFrame_13b   = 0x0c,
    SPI_DataFrame_14b   = 0x0d,
    SPI_DataFrame_15b   = 0x0e,
    SPI_DataFrame_16b   = 0x0f
} SPI_DataFrameSizeDef;
typedef enum SPI_BaudRateDiv
{
    SPI_BaudRateDiv_2   = 0x02,         
    SPI_BaudRateDiv_4   = 0x04,         
    SPI_BaudRateDiv_6   = 0x06,         
    SPI_BaudRateDiv_8   = 0x08,         
    SPI_BaudRateDiv_16  = 0x10,         
    SPI_BaudRateDiv_32  = 0x20,         
    SPI_BaudRateDiv_48  = 0x30,         
    SPI_BaudRateDiv_64  = 0x40,         
    SPI_BaudRateDiv_96  = 0x60,         
    SPI_BaudRateDiv_128 = 0x80,         
    SPI_BaudRateDiv_160 = 0xA0,         
    SPI_BaudRateDiv_192 = 0xC0,         
    SPI_BaudRateDiv_224 = 0xE0,         
    SPI_BaudRateDiv_240 = 0xF0,         
    SPI_BaudRateDiv_250 = 0xFA,         
} SPI_BaudRateDivDef;
#define SPI_BAUD_RATE_DIV(x)    ((x)?(x):(256)) 
typedef enum SPI_ClockPol
{
    SPI_ClockPolarityLow    = 0x0,      
    SPI_ClockPolarityHigh   = 0x1           
} SPI_ClockPolDef;
typedef enum SPI_ClockPhase
{
    SPI_ClockPhaseFirstEdge     = 0x0,      
    SPI_ClockPhaseSecondEdge    = 0x1           
} SPI_ClockPhaseDef;
typedef enum SPI_FrameFormat
{
    SPI_FormatMotorola     = 0x00,      
    SPI_FormatTi           = 0x01,      
    SPI_FormatMicrowire    = 0x02,      
} SPI_FrameFormatDef;
typedef struct
{
    SPI_RoleDef SPI_role;
    SPI_DataFrameSizeDef SPI_dataFrameSize;
    SPI_ClockPolDef SPI_CPOL;
    SPI_ClockPhaseDef SPI_CPHA;
    uint16_t SPI_baudRateDiv;
    SPI_FrameFormatDef SPI_format;
} SPI_InitTypeDef;
__STATIC_INLINE void SPI_EnableSpi(SPI_T* SPIx)
{
    uint32_t tmpreg = 0;
 
    tmpreg = SPIx->CR1;
    tmpreg |= SPI_CR1_SSE_Msk;
    SPIx->CR1 = tmpreg;
}
 
__STATIC_INLINE void SPI_DisableSpi(SPI_T* SPIx)
{
    uint32_t tmpreg = 0;
 
    tmpreg = SPIx->CR1;
    tmpreg &= ~SPI_CR1_SSE_Msk;
    SPIx->CR1 = tmpreg;
}
 
__STATIC_INLINE bool SPI_IsSpiEnabled(SPI_T* SPIx)
{
    uint32_t tmpreg = 0;
 
    tmpreg = SPIx->CR1;
    if(tmpreg & SPI_CR1_SSE_Msk)
        return true;
    else
        return false;
}
 
__STATIC_INLINE void SPI_EnableDmaTx(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->DMACR;
    tmpreg |= SPI_DMACR_TDMAE_Msk;
    SPIx->DMACR = tmpreg;
}
 
__STATIC_INLINE void SPI_DisableDmaTx(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->DMACR;
    tmpreg &= ~SPI_DMACR_TDMAE_Msk;
    SPIx->DMACR = tmpreg;
}
 
__STATIC_INLINE bool SPI_IsDmaTxEnabled(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->DMACR;
    if(tmpreg & SPI_DMACR_TDMAE_Msk)
        return true;
    else
        return false;
}
 
__STATIC_INLINE void SPI_EnableDmaRx(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->DMACR;
    tmpreg |= SPI_DMACR_RDMAE_Msk;
    SPIx->DMACR = tmpreg;
}
 
__STATIC_INLINE void SPI_DisableDmaRx(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->DMACR;
    tmpreg &= ~SPI_DMACR_RDMAE_Msk;
    SPIx->DMACR = tmpreg;
}
 
__STATIC_INLINE bool SPI_IsDmaRxEnabled(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->DMACR;
    if(tmpreg & SPI_DMACR_RDMAE_Msk)
        return true;
    else
        return false;
}
 
__STATIC_INLINE void SPI_SendData(SPI_T* SPIx, uint32_t Data)
{
    SPIx->DR = Data;
}
 
__STATIC_INLINE uint32_t SPI_ReceiveData(SPI_T* SPIx)
{
    return SPIx->DR;
}
 
__STATIC_INLINE void SPI_EnableIrq(SPI_T* SPIx, SPI_IrqDef irq)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->IMSC;
    tmpreg |= irq;
    SPIx->IMSC = tmpreg;
}
 
__STATIC_INLINE void SPI_DisableIrq(SPI_T* SPIx, SPI_IrqDef irq)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->IMSC;
    tmpreg &= ~irq;
    SPIx->IMSC = tmpreg;
}
 
__STATIC_INLINE bool SPI_IsIrqEnabled(SPI_T* SPIx, SPI_IrqDef irq)
{
    uint32_t tmpreg;
 
    tmpreg = SPIx->IMSC;
    if(tmpreg & irq )
        return true;
    else
        return false;
}
 
__STATIC_INLINE SPI_IrqDef SPI_GetMskedActiveIrq(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->MIS;
    tmpreg &= SPI_IRQ_ALL;
 
    return (SPI_IrqDef)tmpreg;
}
 
__STATIC_INLINE bool SPI_IsIrqActive(SPI_T * SPIx, SPI_IrqDef irq)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->MIS;
    if(tmpreg & irq )
        return true;
    else
        return false;
}
 
__STATIC_INLINE bool SPI_IsRawIrqActive(SPI_T * SPIx, SPI_IrqDef irq)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->RIS;
    if(tmpreg & irq )
        return true;
    else
        return false;
}
 
__STATIC_INLINE void SPI_ClearIrq(SPI_T * SPIx, SPI_IrqDef irq)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->ICR;
    tmpreg |= irq ;
    SPIx->ICR = tmpreg;
}
__STATIC_INLINE SPI_IrqDef SPI_GetRawActiveIrq(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->RIS;
    tmpreg &= SPI_IRQ_ALL;
 
    return (SPI_IrqDef)tmpreg;
}
 
__STATIC_INLINE bool SPI_IsTxFifoEmpty(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
    tmpreg = SPIx->SR;
 
    if(tmpreg & SPI_SR_TFE_Msk)
        return true;
    else
        return false;
}
__STATIC_INLINE bool SPI_IsTxFifoFull(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->SR;
 
    if(tmpreg & SPI_SR_TFNF_Msk)
        return false;
    else
        return true;
}
__STATIC_INLINE bool SPI_IsRxFifoEmpty(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->SR;
 
    if(tmpreg & SPI_SR_RFNE_Msk)
        return false;
    else
        return true;
 
}
__STATIC_INLINE bool SPI_IsRxFifoFull(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->SR;
 
    if(tmpreg & SPI_SR_RFF_Msk)
        return true;
    else
        return false;
 
}
__STATIC_INLINE bool SPI_IsBusy(SPI_T* SPIx)
{
    uint32_t tmpreg = 0x00;
 
    tmpreg = SPIx->SR;
    if(tmpreg & SPI_SR_BUSY_Msk)
        return true;
    else
        return false;
}
 
__STATIC_INLINE void SPI_TxLsbEnable(SPI_T* SPIx,bool enable)
{
    (enable) ? (SPIx->CR1 |= SPI_CR1_TX_LSB_EN_Msk) : (SPIx->CR1 &= ~SPI_CR1_TX_LSB_EN_Msk);
}
 
__STATIC_INLINE void SPI_RxLsbEnable(SPI_T* SPIx,bool enable)
{
    (enable) ? (SPIx->CR1 |= SPI_CR1_RX_LSB_EN_Msk) : (SPIx->CR1 &= ~SPI_CR1_RX_LSB_EN_Msk);
}
void SPI_Init(SPI_T* SPIx, SPI_InitTypeDef* SPI_InitStruct);
 
#ifdef __cplusplus
}
#endif
 
#endif /* __PAN_SPI_H__ */