pan_pwm.h

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/*
 * Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0 
 */
 
#ifndef __PAN_PWM_H__
#define __PAN_PWM_H__
 
#ifdef __cplusplus
extern "C"
{
#endif
 
 
#define PWM_CHANNEL_NUM                     (8)   
#define PWM_CH0                 0x0         
#define PWM_CH1                 0x1         
#define PWM_CH2                 0x2         
#define PWM_CH3                 0x3         
#define PWM_CH4                 0x4         
#define PWM_CH5                 0x5         
#define PWM_CH6                 0x6         
#define PWM_CH7                 0x7         
#if 0
#define PWM_TRIGGER_ADC_CNTR_IS_0           PWM_ADCTCTL0_ZPTRGEN0_Msk   
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_D       PWM_ADCTCTL0_CDTRGEN0_Msk   
#define PWM_TRIGGER_ADC_CNTR_IS_CNR         PWM_ADCTCTL0_CPTRGEN0_Msk   
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_U       PWM_ADCTCTL0_CUTRGEN0_Msk   
#endif
 
typedef enum _PWM_ClkDivDef
{
    PWM_CLK_DIV_1   = 4, 
    PWM_CLK_DIV_2   = 0, 
    PWM_CLK_DIV_4   = 1, 
    PWM_CLK_DIV_8   = 2, 
    PWM_CLK_DIV_16  = 3  
} PWM_ClkDivDef;
typedef enum _PWM_AlignedTypeDef
{
    PWM_EDGE_ALIGNED    = 0, 
    PWM_CENTER_ALIGNED  = 1  
} PWM_AlignedTypeDef;
typedef enum _PWM_IntPeriodTypeDef
{
    PWM_PERIOD_INT_UNDERFLOW    = 0, 
    PWM_PERIOD_INT_MATCH_CNR    = 1  
} PWM_IntPeriodTypeDef;
typedef enum _PWM_OperateTypeDef
{
    OPERATION_EDGE_ALIGNED              = 0x01, 
    OPERATION_CENTER_ALIGNED            = 0x02, 
    OPERATION_PRECISE_CENTER_ALIGNED    = 0x04  
} PWM_OperateTypeDef;
typedef enum _PWM_CntModeDef
{
    PWM_CNTMODE_ONE_SHOT    = 0x00, 
    PWM_CNTMODE_AUTO_RELOAD = 0x01  
} PWM_CntModeDef;
__STATIC_INLINE void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
{
    pwm->POEN |= u32ChannelMask;
}
 
__STATIC_INLINE void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
{
    pwm->POEN &= ~u32ChannelMask;
}
 
__STATIC_INLINE void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
{
    // every two channels shares the same setting
    u32ChannelNum >>= 1;
    // set duration
    pwm->DTCTL = (pwm->DTCTL & ~(PWM_DTCTL_DTI01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
    // enable dead zone
    pwm->CTL2 |= (PWM_CTL2_DTCNT01_Msk << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
{
    // every two channels shares the same setting
    u32ChannelNum >>= 1;
    // enable dead zone
    pwm->CTL2 &= ~(PWM_CTL2_DTCNT01_Msk << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_EnableCMPDInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN |= ((1 << PWM_INTEN_CMPDIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_DisableCMPDInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN &= ~((1 << PWM_INTEN_CMPDIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_ClearCMPDIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    pwm->INTSTS = (PWM_INTSTS_CMPDIF0_Msk << u32ChannelNum);
}
 
__STATIC_INLINE uint32_t PWM_GetCMPDIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    return(pwm->INTSTS & (PWM_INTSTS_CMPDIF0_Msk << u32ChannelNum) ? 1 : 0);
}
 
__STATIC_INLINE void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN |= ((1 << PWM_INTEN_PIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN &= ~((1 << PWM_INTEN_PIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    pwm->INTSTS = (PWM_INTSTS_PIF0_Msk << u32ChannelNum);
}
 
__STATIC_INLINE uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    return(pwm->INTSTS & (PWM_INTSTS_PIF0_Msk << u32ChannelNum) ? 1 : 0);
}
 
 
 
__STATIC_INLINE void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN |= ((1 << PWM_INTEN_ZIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN &= ~((1 << PWM_INTEN_ZIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    pwm->INTSTS = (PWM_INTSTS_ZIF0_Msk << u32ChannelNum);
}
 
__STATIC_INLINE uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    return(pwm->INTSTS & (PWM_INTSTS_ZIF0_Msk << u32ChannelNum) ? 1 : 0);
}
//------------------------------------------------------
__STATIC_INLINE void PWM_EnableCMPUInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN |= ((1 << PWM_INTEN_CMPUIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_DisableCMPUInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    (pwm)->INTEN &= ~((1 << PWM_INTEN_CMPUIEN0_Pos) << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_ClearCMPUIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    pwm->INTSTS = (PWM_INTSTS_CMPUIF0_Msk << u32ChannelNum);
}
 
__STATIC_INLINE uint32_t PWM_GetCMPUIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    return (pwm->INTSTS & (PWM_INTSTS_CMPUIF0_Msk << u32ChannelNum) ? 1 : 0);
}
 
__STATIC_INLINE void PWM_EnableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum, PWM_IntPeriodTypeDef IntPeriodType)
{
    pwm->CTL2 &= ~PWM_CTL2_PINTTYPE_Msk;
    pwm->CTL2 |= (IntPeriodType << PWM_CTL2_PINTTYPE_Pos);
    pwm->INTEN = (pwm->INTEN & ~(PWM_INTEN_PIEN0_Msk << u32ChannelNum)) | (PWM_INTEN_PIEN0_Msk << u32ChannelNum) ;   
}
 
__STATIC_INLINE void PWM_DisableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum)
{
    pwm->INTEN &= ~(PWM_INTEN_PIEN0_Msk << u32ChannelNum);
}
 
__STATIC_INLINE void PWM_ClearCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    pwm->INTSTS = (PWM_INTSTS_PIF0_Msk << u32ChannelNum);
}
 
__STATIC_INLINE uint32_t PWM_GetCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
{
    return(pwm->INTSTS & (PWM_INTSTS_PIF0_Msk << u32ChannelNum) ? 1 : 0);
}
 
__STATIC_INLINE void PWM_EnableIndependentMode(PWM_T *pwm)
{
    pwm->CTL2 &= ~PWM_CTL2_MODE_Msk;
}
__STATIC_INLINE void PWM_EnableComplementaryMode(PWM_T *pwm)
{
    pwm->CTL2 = (pwm->CTL2 & ~PWM_CTL2_MODE_Msk) | (1UL << PWM_CTL2_MODE_Pos);
}
 
__STATIC_INLINE void PWM_DisableComplementaryMode(PWM_T *pwm)
{
    pwm->CTL2 &= ~PWM_CTL2_MODE_Msk;
}
 
__STATIC_INLINE void PWM_EnableGroupMode(PWM_T *pwm)
{
    pwm->CTL2 |= PWM_CTL2_GROUPEN_Msk;
}
 
__STATIC_INLINE void PWM_DisableGroupMode(PWM_T *pwm)
{
    pwm->CTL2 &= ~PWM_CTL2_GROUPEN_Msk;
}
 
__STATIC_INLINE void PWM_EnableSyncMode(PWM_T *pwm)
{
    pwm->CTL2 = (pwm->CTL2 & ~PWM_CTL2_MODE_Msk) | (2UL << PWM_CTL2_MODE_Pos);
}
 
__STATIC_INLINE void PWM_DisableSyncMode(PWM_T *pwm)
{
    pwm->CTL2 &= ~PWM_CTL2_MODE_Msk;
}
 
__STATIC_INLINE void PWM_SetPrescaler(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Prescaler)
{
    pwm->CLKPSC = (pwm->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u32Prescaler << ((u32ChannelNum >> 1) * 8));
}
 
__STATIC_INLINE void PWM_ResetPrescaler(PWM_T *pwm, uint32_t u32ChannelNum)
{
    pwm->CLKPSC &= ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8));
}
 
__STATIC_INLINE void PWM_SetDivider(PWM_T *pwm, uint32_t u32ChannelNum, PWM_ClkDivDef Divider)
{
    pwm->CLKDIV = (pwm->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | (Divider << (u32ChannelNum * 4));
}
 
__STATIC_INLINE void PWM_SetCMR(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32CMR)
{
    (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR & 0x0000FFFF)|(*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) & 0xFFFF0000));
}
__STATIC_INLINE void PWM_SetCNR(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32CNR)
{
    (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR));
}
 
__STATIC_INLINE void PWM_SetCMRD(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32CMRD)
{
    (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16)|(*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4))) & 0x0000FFFF));
}
 
__STATIC_INLINE void PWM_SetAlignedType(PWM_T *pwm, uint32_t u32ChannelMask, PWM_AlignedTypeDef AlignedType)
{
    pwm->CTL2 = (pwm->CTL2 & ~PWM_CTL2_CNTTYPE_Msk) | (AlignedType << PWM_CTL2_CNTTYPE_Pos);
}
 
__STATIC_INLINE void PWM_EnableAsymmetricMode(PWM_T *pwm)
{
    pwm->CTL |= PWM_CTL_ASYMEN_Msk;
}
 
__STATIC_INLINE void PWM_DisableAsymmetricMode(PWM_T *pwm)
{
    pwm->CTL &= ~PWM_CTL_ASYMEN_Msk;
}
 
__STATIC_INLINE void PWM_EnablePCA(PWM_T *pwm)
{
    pwm->PCACTL |= PWM_PCACTL_PCAEN_Msk;
}
 
__STATIC_INLINE void PWM_DisablePCA(PWM_T *pwm)
{
    pwm->PCACTL &= ~PWM_PCACTL_PCAEN_Msk;
}
 
__STATIC_INLINE void PWM_SetCntMode(PWM_T *pwm, uint32_t u32ChannelNum, PWM_CntModeDef CntMode)
{
    pwm->CTL = (pwm->CTL & ~(PWM_CTL_CNTMODE0_Msk << (u32ChannelNum * 4))) | ((CntMode << PWM_CTL_CNTMODE0_Pos) << ((u32ChannelNum) * 4));
}
 
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
                                  uint32_t u32ChannelNum, 
                                  uint32_t u32Frequency, 
                                  uint32_t u32DutyCycle,
                                  PWM_OperateTypeDef OperateType);
                                  
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
 
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
 
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
 
void PWM_EnableOutputInverter(PWM_T *pwm, uint32_t u32ChannelMask);
 
void PWM_DisableOutputInverter(PWM_T *pwm, uint32_t u32ChannelMask);
 
 
#if 0
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
#endif
 
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* __PAN_PWM_H__ */