pan_adc.h

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/*
 * Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0 
 */
 
#ifndef __PAN_ADC_H__
#define __PAN_ADC_H__
 
#ifdef __cplusplus
extern "C"
{
#endif
 
 
#define ADC_INPUTRANGE_HIGH             (1UL)                               
#define ADC_INPUTRANGE_LOW              (0UL)                               
#define ADC_CH8_EXT                     (0UL)                               
#define ADC_CH8_BGP                     (ADC_CHEN_CH8SEL_Msk)               
#define ADC_CMP0_LESS_THAN              (0UL << ADC_CMP0_CMPCOND_Pos)       
#define ADC_CMP1_LESS_THAN              (0UL << ADC_CMP1_CMPCOND_Pos)       
#define ADC_CMP0_GREATER_OR_EQUAL_TO    (1ul << ADC_CMP0_CMPCOND_Pos)       
#define ADC_CMP1_GREATER_OR_EQUAL_TO    (1ul << ADC_CMP1_CMPCOND_Pos)       
#define ADC_TRIGGER_BY_EXT_PIN          (0UL << ADC_CTL_HWTRGSEL_Pos)       
#define ADC_TRIGGER_BY_PWM              (ADC_CTL_HWTRGSEL_Msk)              
#define ADC_FALLING_EDGE_TRIGGER        (0UL << ADC_CTL_HWTRGCOND_Pos)      
#define ADC_RISING_EDGE_TRIGGER         (ADC_CTL_HWTRGCOND_Msk)             
#define ADC_ADIF_INT                    (ADC_STATUS_ADIF_Msk)               
#define ADC_CMP0_INT                    (ADC_STATUS_ADCMPIF0_Msk)           
#define ADC_CMP1_INT                    (ADC_STATUS_ADCMPIF1_Msk)           
#define ADC_FIFO_FULL_INT               (ADC_STATUS_INTFLG_FULL_Msk)        
#define ADC_FIFO_EMPTY_INT              (ADC_STATUS_INTFLG_EMPTY_Msk)       
#define ADC_FIFO_OVER_INT               (ADC_STATUS_INTFLG_OVER_Msk)        
#define ADC_FIFO_HALF_INT               (ADC_STATUS_INTFLG_HALF_Msk)        
#define ADC_SAMPLE_CLOCK_0              (0UL)                               
#define ADC_SAMPLE_CLOCK_1              (1UL)                               
#define ADC_SAMPLE_CLOCK_2              (2UL)                               
#define ADC_SAMPLE_CLOCK_4              (3UL)                               
#define ADC_SAMPLE_CLOCK_8              (4UL)                               
#define ADC_SAMPLE_CLOCK_16             (5UL)                               
#define ADC_SAMPLE_CLOCK_32             (6UL)                               
#define ADC_SAMPLE_CLOCK_64             (7UL)                               
#define ADC_SAMPLE_CLOCK_128            (8UL)                               
#define ADC_SAMPLE_CLOCK_256            (9UL)                               
#define ADC_SAMPLE_CLOCK_512            (10UL)                              
#define ADC_SAMPLE_CLOCK_1024           (11UL)                              
#define ADC_SEQMODE_TYPE_23SHUNT        (0UL)                               
#define ADC_SEQMODE_TYPE_1SHUNT         (1UL)                               
#define ADC_SEQMODE_MODESELECT_CH01     (0UL)                               
#define ADC_SEQMODE_MODESELECT_CH12     (1UL)                               
#define ADC_SEQMODE_MODESELECT_CH02     (2UL)                               
#define ADC_SEQMODE_MODESELECT_ONE      (3UL)                               
#define ADC_SEQMODE_PWM0_RISING         (0UL)                               
#define ADC_SEQMODE_PWM0_CENTER         (1UL)                               
#define ADC_SEQMODE_PWM0_FALLING        (2UL)                               
#define ADC_SEQMODE_PWM0_PERIOD         (3UL)                               
#define ADC_SEQMODE_PWM2_RISING         (4UL)                               
#define ADC_SEQMODE_PWM2_CENTER         (5UL)                               
#define ADC_SEQMODE_PWM2_FALLING        (6UL)                               
#define ADC_SEQMODE_PWM2_PERIOD         (7UL)                               
#define ADC_SEQMODE_PWM4_RISING         (8UL)                               
#define ADC_SEQMODE_PWM4_CENTER         (9UL)                               
#define ADC_SEQMODE_PWM4_FALLING        (10UL)                              
#define ADC_SEQMODE_PWM4_PERIOD         (11UL)                              
#define ADC_SEQMODE_PWM6_RISING         (12UL)                              
#define ADC_SEQMODE_PWM6_CENTER         (13UL)                              
#define ADC_SEQMODE_PWM6_FALLING        (14UL)                              
#define ADC_SEQMODE_PWM6_PERIOD         (15UL)                              
#define ADC_COMPARATOR_0                (0) 
#define ADC_COMPARATOR_1                (1) 
#define ADC_FIFO_TRIG_LEVEL_HALF        (0) 
#define ADC_FIFO_TRIG_LEVEL_FULL        (1) 
__STATIC_INLINE uint32_t ADC_GetConversionData(ADC_T *ADCx)
{
    return (ADCx->DAT & ADC_DAT_RESULT_Msk);
} 
 
__STATIC_INLINE bool ADC_StatusFlag(ADC_T *ADCx,uint32_t IntMask)
{
    return (ADCx->STATUS & IntMask)?(true):(false);
}
 
__STATIC_INLINE void ADC_ClearStatusFlag(ADC_T *ADCx,uint32_t IntMask)
{
    ADCx->STATUS |= IntMask;
}
__STATIC_INLINE void ADC_IntMask(ADC_T *ADCx,uint32_t IntMask,FunctionalState NewState)
{
    (NewState == DISABLE)?(ADCx->STATUS |= IntMask):(ADCx->STATUS &= ~IntMask);
}
 
__STATIC_INLINE bool ADC_IsIntOccured(ADC_T *ADCx,uint32_t IntMask)
{
    return (ADCx->STATUS & IntMask)?(true):(false);
}
 
__STATIC_INLINE void ADC_ClearIntFlag(ADC_T *ADCx,uint32_t IntMask)
{
    ADCx->STATUS = ADCx->STATUS | IntMask;
}                                                                       
__STATIC_INLINE bool ADC_IsBusy(ADC_T *ADCx)
{
    return (ADCx->STATUS & ADC_STATUS_BUSY_Msk)?(true):(false);
}     
__STATIC_INLINE bool ADC_IsDataOverrun(ADC_T *ADCx)
{
    return (ADCx->STATUS & ADC_STATUS_OV_Msk)?(true):(false);
} 
__STATIC_INLINE bool ADC_IsDataValid(ADC_T *ADCx)
{
    return (ADCx->STATUS & ADC_STATUS_VALID_Msk)?(true):(false);
}
__STATIC_INLINE void ADC_PowerDown(ADC_T *ADCx)
{
    ADCx->CTL = ADCx->CTL & ~ADC_CTL_ADCEN_Msk;
} 
__STATIC_INLINE void ADC_PowerOn(ADC_T *ADCx)
{
    ADCx->CTL  = ADCx->CTL | ADC_CTL_ADCEN_Msk;
}
__STATIC_INLINE void ADC_SequentialModeDisable(ADC_T *ADCx)
{
    ADCx->SEQCTL  = ADCx->SEQCTL & ~ADC_SEQCTL_SEQEN_Msk;
}
__STATIC_INLINE void ADC_Trigger2Select(ADC_T *ADCx,FunctionalState NewState)
{
    (NewState == ENABLE)?(ADCx->SEQCTL |= ADC_SEQCTL_TRG_SEL_Msk):(ADCx->SEQCTL &= ~ADC_SEQCTL_TRG_SEL_Msk);
}
                                                                                                                                     
__STATIC_INLINE void ADC_DisableCompare0(ADC_T *ADCx)
{
    ADCx->CMP0  = 0;
}
 
__STATIC_INLINE void ADC_DisableCompare1(ADC_T *ADCx)
{
    ADCx->CMP1  = 0;
}
 
__STATIC_INLINE void ADC_StartConvert(ADC_T *ADCx)
{
    ADCx->CTL  = ADCx->CTL | ADC_CTL_SWTRG_Msk;
}
__STATIC_INLINE void ADC_StopConvert(ADC_T *ADCx)
{
    ADCx->CTL  &= ~ADC_CTL_SWTRG_Msk;
}
 
__STATIC_INLINE void ADC_TestModeEnable(ADC_T *ADCx)
{
    ADCx->CTL2  |= ADC_CTL2_TESTMODE_Msk;
}
__STATIC_INLINE void ADC_TestModeDisable(ADC_T *ADCx)
{
    ADCx->CTL2  &= ~ADC_CTL2_TESTMODE_Msk;
}
__STATIC_INLINE void ADC_DmaModeEnable(ADC_T *ADCx,FunctionalState NewState)
{
    (NewState == ENABLE)?(ADCx->CTL2 |= ADC_CTL2_DMA_EN_Msk):(ADCx->CTL2 &= ~ADC_CTL2_DMA_EN_Msk);
}
 
__STATIC_INLINE void ADC_SetClockDivider(ADC_T *ADCx,uint32_t Divider)
{
    ADCx->CTL2  = (ADCx->CTL2 & ~ADC_CTL2_CLKDIV_Msk) | (Divider << ADC_CTL2_CLKDIV_Pos);
}
 
__STATIC_INLINE void ADC_Open(ADC_T *ADCx,uint32_t ChMask)
{
    ADCx->CHEN  = (ADCx->CHEN & ~ADC_CHEN_ALL_Msk) | ChMask;
}
__STATIC_INLINE void ADC_SelInputRange(ADC_T *ADCx,uint32_t EnableHigh)
{
    ADCx->CTL2 = (ADCx->CTL2 & ~ADC_SEL_VREF_Msk) | (EnableHigh << ADC_SEL_VREF_Pos);
}
__STATIC_INLINE void ADC_TriggerDelay(ADC_T *ADCx,uint32_t Data)
{
    ADCx->TRGDLY = Data;
}
__STATIC_INLINE void ADC_SetExtraSampleTime(ADC_T *ADCx,uint32_t SampleTime)
{
    ADCx->EXTSMPT = (ADCx->EXTSMPT & ~ADC_EXTSMPT_EXTSMPT_Msk) | SampleTime;
}
 
__STATIC_INLINE bool ADC_IsOneChConvertEnd(ADC_T *ADCx)
{
    return (ADCx->STATUS & ADC_STATUS_ONE_CH_FLAG_Msk)?(true):(false);
}
 
__STATIC_INLINE void ADC_ClearByHw(ADC_T *ADCx,FunctionalState NewState)
{
    (NewState == ENABLE)?(ADCx->STATUS |= ADC_STATUS_ONE_CH_CLR_SEL_Msk):(ADCx->STATUS &= ~ADC_STATUS_ONE_CH_CLR_SEL_Msk);
}
 
__STATIC_INLINE void ADC_LeftShiftEn(ADC_T *ADCx,FunctionalState NewState)
{
    (NewState == ENABLE)?(ADCx->LS_CTL |= ADC_LS_CTL_LS_EN_Msk):(ADCx->LS_CTL &= ~ADC_LS_CTL_LS_EN_Msk);
}
 
__STATIC_INLINE uint32_t ADC_GetLeftShiftData(ADC_T *ADCx)
{
    return ((ADCx->LS_CTL & ADC_LS_CTL_LS_DAT_Msk) >> ADC_LS_CTL_LS_DAT_Pos);
}
__STATIC_INLINE void ADC_SubtractBiasEn(ADC_T *ADCx,FunctionalState NewState)
{
    (NewState == ENABLE)?(ADCx->SUB_CTL |= ADC_SUB_CTL_BIAS_EN_Msk):(ADCx->SUB_CTL &= ~ADC_SUB_CTL_BIAS_EN_Msk);
}
 
__STATIC_INLINE void ADC_SetBiasData(ADC_T *ADCx,uint32_t BiasData)
{
     ADCx->SUB_CTL = (ADCx->SUB_CTL & ~ADC_LS_CTL_LS_DAT_Msk) | (BiasData << ADC_LS_CTL_LS_DAT_Pos);
}
 
__STATIC_INLINE uint32_t ADC_GetLeftBiasData(ADC_T *ADCx)
{
     return ADCx->DATA_SUB & ADC_DAT_SUB_LEFT_BIAS_Msk;
}
 
__STATIC_INLINE void ADC_SetFifoTrigLevel(ADC_T *ADCx,uint8_t Level)
{
     ADCx->FIFO_CTL = (ADCx->FIFO_CTL & ~ADC_FIFO_CTL_HALF_OR_FULL_Msk) | ((Level << ADC_FIFO_CTL_HALF_OR_FULL_Pos)|ADC_FIFO_CTL_EN_Msk);
}
 
__STATIC_INLINE uint32_t ADC_GetFifoPopData(ADC_T *ADCx)
{
     return ADCx->POP_DATA & ADC_FIFO_POP_DAT_Msk;
}
 
__STATIC_INLINE void ADC_SeqModeOneChEn(ADC_T *ADCx,FunctionalState NewState)
{
    (NewState)?(ADCx->SEQCTL |= ADC_SEQCTL_ONE_CH_EN_Msk):(ADCx->SEQCTL &= ~ADC_SEQCTL_ONE_CH_EN_Msk);
}
 
__STATIC_INLINE void ADC_SeqModeChSelect(ADC_T *ADCx,uint8_t Ch)
{
    ADCx->SEQCTL = (ADCx->SEQCTL & ~ADC_SEQCTL_ONE_CH_SEL_Msk) | (Ch << ADC_SEQCTL_ONE_CH_SEL_Pos);
}
 
void ADC_Disable(ADC_T *ADCx);
 
void ADC_Close(void);
 
void ADC_EnableHWTrigger(ADC_T *ADCx,
                         uint32_t Source,
                         uint32_t Param);
                         
void ADC_DisableHWTrigger(ADC_T *ADCx);
 
void ADC_EnableInt(ADC_T *ADCx, uint32_t Mask);
 
void ADC_DisableInt(ADC_T *ADCx, uint32_t Mask);
                   
void ADC_SeqModeEnable(ADC_T *ADCx, uint32_t SeqTYPE, uint32_t ModeSel);
 
void ADC_SeqModeTriggerSrc(ADC_T *ADCx, uint32_t SeqModeTriSrc);
 
void ADC_CompareEnable(ADC_T *ADCx,
                       uint32_t ChNum,
                       uint32_t CmpCondition,
                       uint32_t CmpData,
                       uint32_t MatchCnt,
                       uint32_t CmpSelect);
                       
void ADC_SeqOneChModeConfig(ADC_T *ADCx, 
                            uint32_t Trig,
                            uint8_t Level,
                            uint8_t DmaEn,
                            uint8_t HwClrEN,
                            uint8_t AdcCh);
#ifdef __cplusplus
}
#endif
 
#endif /* __PAN_ADC_H__ */