pan_pri_rf.h

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/*
 * Copyright (C) 2021 Panchip Technology Corp. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0 
 */
 
 *****************************************************************************/ 
#ifndef __PAN_PRI_RF_H__
#define __PAN_PRI_RF_H__
#ifdef __cplusplus
extern "C"
{
#endif
 
#define PRI_RF_MODE_SEL_TX              (0)   
#define PRI_RF_MODE_SEL_RX              (1)   
#define PRI_RF_MODE_SEL_TRX             (2)   
#define PRI_RF_ADDR_BYTE_LEN_INVALID    (0)   
#define PRI_RF_ADDR_BYTE_LEN_3          (1)     
#define PRI_RF_ADDR_BYTE_LEN_4          (2)     
#define PRI_RF_ADDR_BYTE_LEN_5          (3)     
#define PRI_RF_CHIP_MODE_INVALID        (0)     
#define PRI_RF_CHIP_MODE_BLE            (1)       
#define PRI_RF_CHIP_MODE_297            (2)       
#define PRI_RF_CHIP_MODE_NORDIC         (3)     
#define REG_FILE_OFST                       0x0000    
#define SEQ_RAM_OFST                        0x1000    
#define LIST_RAM_OFST                       0x8000    
#define TX_RX_RAM_OFST                      0x8200    
#define CTE_IQ_RAM_OFST                     0xB7FC    
#define LLHWC_READ32_REG(base_addr, reg_ofst) \
        (*(volatile uint32_t *)((0x50020000) + (base_addr) + (reg_ofst)))
#define LLHWC_WRITE32_REG(base_addr, reg_ofst, data) \
            (*(volatile uint32_t *)(((0x50020000) + (base_addr) + (reg_ofst))) = (data))
#define READ_4_BYTES(pckt, pos) (((uint32_t) (pckt)[pos]) | \
                                (((uint32_t) (pckt)[pos + 1]) << 8) | \
                                (((uint32_t) (pckt)[pos + 2]) << 16) | \
                                (((uint32_t) (pckt)[pos + 3]) << 24))
 
#define PRI_RF_WRITE_REG_VALUE(base,Reg,Func,Value)     \
        (base->Reg = (base->Reg & ~(Reg##_##Func##_Msk)) | ((Value << Reg##_##Func##_Pos) & Reg##_##Func##_Msk))
#define PRI_RF_READ_REG_VALUE(base,Reg,Func)     \
        ((base->Reg & (Reg##_##Func##_Msk)) >> Reg##_##Func##_Pos)
#define PRI_RF_SET_FUNC_ENABLE(base,Reg,Func,State)     \
        ((State == ENABLE) ? (base->Reg |= Reg##_##Func##_Msk) : (base->Reg &= ~Reg##_##Func##_Msk))
__STATIC_INLINE void PRI_RF_AutoAnlsPayloadEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,DPY_EN,NewState);
}
 
__STATIC_INLINE void PRI_RF_CrcCheckEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,CRC_EN,NewState);
}
 
__STATIC_INLINE void PRI_RF_Crc16Select(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,CRC_SEL16,NewState);
}
__STATIC_INLINE void PRI_RF_ScambleEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,SCR_EN,NewState);
}
 
__STATIC_INLINE void PRI_RF_NordicEnhanceEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,NORDIC_ENHANCE,NewState);
}
__STATIC_INLINE uint8_t PRI_RF_IsNordicEnhance(PRI_RF_T *rf)
{
    return PRI_RF_READ_REG_VALUE(rf,R00_CTL,NORDIC_ENHANCE);
}
__STATIC_INLINE void PRI_RF_EnhanceEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,ENHANCE,NewState);
}
__STATIC_INLINE uint8_t PRI_RF_IsEnhance(PRI_RF_T *rf)
{
    return PRI_RF_READ_REG_VALUE(rf,R00_CTL,ENHANCE);
}
__STATIC_INLINE void PRI_RF_BandWidth2mSel(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,BW_MODE,NewState);
}
 
__STATIC_INLINE void PRI_RF_ChipModeSel(PRI_RF_T *rf,uint8_t modeSel)   
{
    PRI_RF_WRITE_REG_VALUE(rf,R00_CTL,CHIP_MODE,modeSel);
}
__STATIC_INLINE uint8_t PRI_RF_GetChipMode(PRI_RF_T *rf)    
{
    return PRI_RF_READ_REG_VALUE(rf,R00_CTL,CHIP_MODE);
}
 
__STATIC_INLINE void PRI_RF_RxAckEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,RX_ACK_PAYLOAD_EN,NewState);
}
__STATIC_INLINE uint8_t PRI_RF_IsRxAckEn(PRI_RF_T *rf)
{
    return (rf->R00_CTL & R00_CTL_RX_ACK_PAYLOAD_EN_Msk) >> R00_CTL_RX_ACK_PAYLOAD_EN_Pos;
}
__STATIC_INLINE void PRI_RF_TxNoAckEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,TX_NOACK_EN,NewState);
}
__STATIC_INLINE uint8_t PRI_RF_IsTxNoAckEn(PRI_RF_T *rf)
{
    return (rf->R00_CTL & R00_CTL_TX_NOACK_EN_Msk) >> R00_CTL_TX_NOACK_EN_Pos;
}
 
__STATIC_INLINE void PRI_RF_TrxFuncSel(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R00_CTL,PRI_RX,NewState);
}
 
__STATIC_INLINE uint8_t PRI_RF_IsRxSel(PRI_RF_T *rf)
{
    return PRI_RF_READ_REG_VALUE(rf,R00_CTL,PRI_RX);
}
__STATIC_INLINE void PRI_RF_ClearAllIrqEn(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R01_INT_CTL,IRQ_CLR_EN,NewState);
}
 
 
__STATIC_INLINE void PRI_RF_IntMask(PRI_RF_T *rf,uint32_t msk,FunctionalState NewState)
{
    (NewState)?(rf->R01_INT_CTL |= msk):(rf->R01_INT_CTL &= ~msk);
}
 
__STATIC_INLINE bool PRI_RF_IntFlag(PRI_RF_T *rf,uint32_t msk)
{
    return (rf->R01_INT_CTL & msk)?(true):(false);
}
 
__STATIC_INLINE void PRI_RF_ForceExitRx(PRI_RF_T *rf,FunctionalState NewState)
{
    PRI_RF_SET_FUNC_ENABLE(rf,R01_INT_CTL,EXIT_RX,NewState);
}
 
__STATIC_INLINE void PRI_RF_SetTrxTransWaitTime(PRI_RF_T *rf,uint16_t time)
{
    PRI_RF_WRITE_REG_VALUE(rf,R02_TMR_CTL,TRX_TRANS_WAIT_TIME,time);
}
 
void ana_prf_ldo_en(void);
void ana_prf_ldo_dis(void);
 
void PRI_RF_SetTrxPayloadLen(PRI_RF_T *rf,uint8_t mode,uint8_t len);
 
bool PRI_RF_SetAddrByteLen(PRI_RF_T *rf,uint8_t len);
 
void PRI_RF_SetPidManualEn(PRI_RF_T *rf,uint8_t pid);
 
void PRI_RF_SetRxWaitTime(PRI_RF_T *rf,uint16_t time);
 
void PRI_RF_SetTrxAddr(PRI_RF_T *rf,uint8_t mode,uint32_t *addr);
 
void PRI_RF_SetTrxRamStartAddr(PRI_RF_T *rf,uint8_t mode,uint32_t addr);
 
bool PRI_RF_IsTrxRamReady(PRI_RF_T *rf,uint8_t mode);
 
void PRI_RF_SetTrxRamReady(PRI_RF_T *rf,uint8_t mode,uint8_t ready);
 
 
#ifdef __cplusplus
}
#endif
 
#endif /* __PRI_RF_H__ */